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designed for pulse-width-modulated (pwm) control of dc motors, the A4956 is capable of 50 v operation and provides gate drive for an all n-channel external mosfet bridge. input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied pwm control signals. internal synchronous rectification control circuitry is provided to lower power dissipation during pwm operation. internal circuit protection includes vds protection, thermal shutdown with hysteresis, undervoltage monitoring of vbb, and crossover-current protection. the A4956 is supplied in a low-profile 44 mm, 20-contact qfn package (suffix es) and a 20-lead etssop (suffix lp), both with exposed thermal pad. A4956-ds, rev. 1 ? phase/enable/mode control logic ? overcurrent indication ? adjustable of f-time and blank-time ? adjustable current limit ? adjustable gate drive ? synchronous rectification ? internal uvlo ? crossover -current protection ? mosfet vds protection ? v oltage output proportional to load current ? decay-mode selection for external pwm ? A4956k is aec-q100 grade 1 qualified ? commercial temperature grade (A4956g: C40c to 105c) ? automotive temperature grade (A4956k: C40c to 1 25c) full-bridge pwm gate driver packages: functional block diagram not to scale A4956 charge pump vreg uvlo tsd iset rc mode phase enable standby control logic vcp gate drive vcp vbb gha ghb sb sa cp1 cp2 ocln aiout vref 10 10 ocl filter + ? gla glb sense gnd system controller optional 0.1 f 0.1 f vin gha sa gla r sense inrush current limit = v/ 10 * r ref sense hold features and benefits description 20-pin qfn (suffix es) with exposed thermal pad 20-pin etssop (suffix lp) with exposed thermal pad
2 absolute maximum ratings characteristic symbol notes rating unit load supply voltage v bb 50 v motor outputs sx sx C sense; vbb C sx C2 to 52 v sense v sense C0.5 to 0.5 v t w < 500 ns C4 to 4 v ocln v ocln C0.3 to 5.5 v vref v ref C0.3 to 5.5 v iset v iset C0.3 to 5.5 v aiout v aiout C0.3 to 5.5 v logic input voltage range v in phase, enable, mode C0.3 to 5.5 v junction temperature t j 150 oc storage temperature range t s C55 to 150 oc operating temperature range t a range g C40 to 105 oc range k C40 to 125 oc selection guide part number ambient temp range packing notes A4956gestr-t C40oc to 105oc 1500 pieces per 7-in. reel A4956glptr-t C40oc to 105oc 4000 pieces per 13-in. reel A4956klptr-t C40oc to 125oc 4000 pieces per 13-in. reel aec-q100 qualified thermal characteristics (may require derating at maximum conditions, see application information) characteristic symbol test conditions* value unit es package r ja 4-layer pcb, 1 in 2 cu 37 oc/w lp package 4-layer pcb, 1 in 2 cu 28 oc/w *power dissipation and thermal limits must be observed. specifications full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 terminal list table name number function es package lp package iset 1 8 terminal to set gate drive current mode 2 9 digital mode input sense 3 10 sense resistor connection, low-side gate return glb 4 11 gate driver gla 5 12 gate driver ghb 6 13 gate driver sb 7 14 high-side bridge reference gha 8 15 gate driver sa 9 16 high-side bridge reference vcp 10 17 charge pump reservoir cap connection cp2 11 18 charge pump terminal vbb 12 19 supply voltage cp1 13 20 charge pump terminal gnd 14 1 ground aiout 15 2 analog output proportional to v sense ocln 16 3 ocp and ovp output flag, open drain vref 17 4 analog ocp reference input enable 18 5 digital enable input phase 19 6 digital phase input rc 20 7 terminal to set blank- and off-time pad C C 1 2 3 4 5 11 12 13 14 15 6 7 8 9 10 16 17 18 19 20 iset mode sense glb gla ghb sb gha sa vcp cp2 vbb cp1 gnd pa d aiout ocln vref enable phase rc package es, 20-pin qfn pin-outs 1 2 3 4 5 11 12 13 14 15 6 7 8 9 10 16 17 18 19 20 iset mode sense glb gla ghb sb gha sa pa d vcp cp2 vbb cp1 gnd aiout ocln vref enable phase rc package lp, 20-pin etssop pin-outs full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 characteristics symbol test conditions min. typ. max. unit vbb supply current i bb C 6 10 ma i bb sleepn = low, standby mode C C 5 a gate drive high-side gate drive output gh relative to v bb , i gate = 200 a, vbb = 8 to 50 v 6.5 6.8 7.5 v relative to v bb , i gate = 200 a, vbb = 5.5 v C 5.2 C low-side gate drive output gl i gate = 200 a, vbb = 8 to 50 v 6.5 6.8 7.5 v i gate = 200 a, vbb = 5.5 v C 5.4 C gate drive pull-up current i gpu r iset = 30 k?; gh = gl = 4 v 21 30 39 ma gate drive pull-down current i gpd r iset = 30 k?; gh = gl = 4 v 47 68 89 ma dead-time t dt C 1000 C ns passive pull-down resistance r gpd 30 50 70 k? logic input and output logic output voltage v ocln i = 2 ma, overcurrent detected C 0.2 0.3 v logic output leakage i ocln v = 5 v, normal operation C C 5 a pwm current limit flag timer t ocln 300 500 600 us logic input voltage v ih 2.0 C C v v il C C 0.8 v v il(standby) standby mode, enable input C C 0.4 v logic input hysteresis v hys C 320 C mv logic input pull-down resistor r pd 30 50 70 k? vref input current i vref v ref = 2.5 v -5 < 1 5 a vref input range v ref 0 C 2.5 v current gain a v vref/ v sense , vref = 2.5 v 9.5 C 10.5 v/v input offset, sense v ossense C10 C 10 mv fixed off-time t off r rc = 30 k?, c rc = 1 nf C 30 C s percent fast decay p fd internal pwm chop C 13 C % blank-time t blk r rc = 30 k?, c rc = 1 nf 2.1 3 3.9 s standby timer 0.7 1.0 1.3 ms power-up delay tpu time until outputs are enabled C 50 300 s aiout gain a iout aiout/v sense , v sense = 50 to 200 mv 9 10 11 v/v input offset, aiout v osaiout C15 C 15 mv sample-and-hold accuracy sh acc C 15 C mv sample-and-hold droop rate v droop C C 1 mv/s aiout output impedance rout aiout 0.75 1.00 1.45 k? protection circuits uvlo enable threshold uvlo vbb v bb rising 5.10 5.25 5.40 v uvlo hysteresis uvlo hys 200 300 350 mv vds threshold vds thres C 2 C v thermal shutdown temperature t jtsd temperature increasing. 150 165 185 c thermal shutdown hysteresis t j recovery = t jtsd C t j C 30 C c 1 specifed limits are tested at a single temperature and assured over operating temperature range by design and characterization 2 target trip level = v dsth = v drain - sx (high side on) or v dsth = sx - sense (low side on) electrical characteristics : valid for temperature range g version at t j = 25c and for temperature range k version at t j = C40c to 150c, v bb = 5.5 to 50 v, unless otherwise specifed full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 control logic phase enable mode 10 v sense > v ref outa outb function x 0 (>1ms) x x z z sleep (standby) mode 0 0 (<1ms) 0 false h l en chop, fast decay sr * 1 0 (<1ms) 0 false l h en chop, fast decay sr * 0 1 x false l h reverse 1 1 x false h l forward x 0 (<1ms) 1 false l l slow decay sr (brake) 0 1 x true h/l l internal chop reverse, mixed decay * 1 1 x true l h/l internal chop forward, mixed decay * * in fast decay, outputs change to high-z state when load current approaches zero, to prevent reversal of current. i= v/ ocl ref sense r/ 10 i_out ocln t ocln ocln output flag ocln output function is described in the functional description section. aa bb cd d 300 s aiout v sense 0 v 0 v v= vref/10 sense enable mode aiout output a. internal ocl chop. aiout holds while sense voltage varies during the mixed-decay off-time. b. enable chop, mode = high (slow decay). aiout holds while sense voltage drops to 0 v during slow decay. c. slow-decay timeout. aiout is forced to 0 v 300 s after enable goes low. d. enable chop, mode = low (fast decay). aiout tracks v sense and thus is clamped at 0 v during fast decay. full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 functional description device operation the A4956 is designed to operate dc motors. the output drivers are capable of 50 v with gate-driver capability for an all n-chan- nel external mosfet h-bridge. control logic includes syn- chronous rectification to reduce power dissipation. current limit is regulated by fixed off-time pulse-width-modulated (pwm) control circuitry. internal pwm current control peak current is regulated by monitoring the voltage on an exter- nal sense resistor. i= peak v ref (10 r) sense when the peak current is exceeded, the source driver turns off for a fixed period t off to chop the current. the outputs operate in mixed-decay mode during t off . refer to the fixed off-time setting section to set t off . the internal current-sense circuit is ignored for t blank after pwm transitions. the comparator output is blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, or switching transients related to the capacitance of the load, or both. refer to the blank-time setting section to set t blank . brake it is important to note that the internal pwm current control circuit will not limit the current when braking, since the current does not flow through the sense resistor. the maximum current can be approximated by v bemf / r motor . care should be taken to ensure that the maximum ratings of the external mosfet are not exceeded in worst-case braking situations of high speed and high inertial loads. iset a resistor from iset terminal to ground sets the magnitude of the gate current. the sink and source current ratios are fixed at approximately 2-to-1 where the pull-down current is approxi- mately two times the pull-up current. r iset should be between 20 and 150 k. the formula for determining the gate drive is: i (ma) = gate_hs 900 r( k) iset 1.9 + i (ma) = 3.5 + gate_ls 1700 r( k) iset rc the rc terminal is used to set both fixed off-time and blank-time for the internal pwm current control. refer to the following three sections to select rc component values. fixed off-time setting the internal pwm current-control circuitry uses a one-shot to control the time the drivers remain off. the one-shot off-time (t off ) is determined by the selection of an external resistor and capacitor connected from the rc timing terminal to ground. the off-time, over a range of values of c rc = 470 to 1500 pf and r rc = 12 to 100 k, is approximated by: t off rc rc = r c+ dead time blank-time setting this circuit blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry or by an external pwm chop command. the comparator blanking time, t blank , is determined by the selection of an exter- nal resistor and capacitor connected from the rc timing terminal to ground, and is approximated by: t blank rc = 2.6 s c (nf) e (3.6/r (k)) rc mode the input terminal mode is used to select the bridge behavior when the enable input is brought low. slow-decay or fast- decay mode can be selected. a logic high on the terminal puts the device in slow-decay mode. slow decay in slow-decay mode, the low-side switch stays on and the high-side switch turns off. due to the synchronous rectification feature, the complementary low-side switch turns on after a dead- time. fast decay sr in fast-decay mode, the high-side and low-side switches turn off, and the complementary pair of switches is turned on, effectively reversing the voltage polarity across the motor winding. mixed decay when the peak current is reached, as set by the sense resistor and voltage on vref, the pwm current limiter initiates an off-time. the off-time is determined by the resistor and capacitor on the rc terminal. in mixed-decay mode, the driver will initiate a fast decay, after a dead-time, for 13% of the programmed off-time. full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 after the fast-decay time expires, the bridge will switch to slow decay for the remaining off-time. when the bridge is operating in fast decay, it will internally prevent current reversal by putting the bridge in a high-z state if the current through the sense resis- tor falls close to zero. ocln output an open drain logic output will be driven low to indicate system operation. the ocln terminal is driven low under two condi- tions: 1. when the system is limiting current to value set by vref and r sense . once overcurrent events are no longer detected, the A4956 will release the indication after a time t ocln . 2. when a vds fault is detected, the ocln terminal is driven low. it is released when the fault is reset. the ocln terminal, in combination with the aiout terminal, can provide valuable information about how the system is behav- ing: ? overcurrent events can indicate a motor stall condition, in which case the system controller can respond to the fault condition by reducing pwm duty . when ocln is low and the voltage on aiout is greater than 0 v , the controller is actively limiting current with the internal, fixed off-time pwm current limiter. ? in the case of a vds fault, the ocln terminal is also driven low, but the aiout voltage will be 0 v , because the bridge has been disabled. this notifies the user that a vds fault has occurred and the driver has been disabled. aiout an analog output can be used to monitor current through the external sense resistor (if used). the sense voltage is gained by a factor of 10 and fed to the aiout terminal. a sample-and-hold circuit is used to capture the voltage across the sense resistor and holds it during periods when the voltage is not representative of the current in the motor. the aiout output diagram illustrates when the voltage is held. the held voltage will droop at a rate equal to v droop . in the case of a vds fault on the bridge, the aiout terminal will be discharged to zero volts. charge pump the charge pump is used to generate a supply above vbb to drive the high-side mosfets. the vcp voltage is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. mosfet vds protection the drain-to-source voltage is monitored across the mosfet any time the mosfet is on. if the voltage across the mosfet exceeds vds thres , the bridge is disabled and latched off. in order to prevent false vds faults, the vds monitor is blanked immediately after any mosfet is turned on. the vds monitor waits for a blank-time defined by the components on the rc ter- minal before monitoring the vds level. during the off-time when sr is active, vds blanking is fixed at 1 s. vds fault when a vds fault occurs, and the bridge is disabled, and the fault is latched, the ocln terminal is immediately driven low. the latch can only be reset by going into standby or by dropping vbb below the uvlo threshold. standby mode low power standby mode is activated when enable is held logic low for t stb (typically 1 ms). standby mode disables most of the internal circuitry , including the charge pump and internal regulator. when coming out of standby mode, the A4956 requires up to 300 s before the outputs can respond to input commands. tsd if the die temperature increases to approximately t tsd , the full bridge outputs will be disabled until the internal temperature falls below t tsd minus a hysteresis level of t hys . fault shutdown in the event of a fault due to excessive junction temperature, or low voltage on vcp or vbb, the outputs of the device are disabled until the fault condition is removed. at power-up, the uvlo circuit disables the drivers until the uvlo thresholds are exceeded. full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 terminal circuit diagrams vcp sx gnd gnd gnd gnd gnd gnd gnd gnd 6.7 v 10 v 8 v 8 v 8 v 6.7 v enable phase riset aiout vref mode rc ocln vbb sense sense glx ghx sx vcp gnd gnd vcp cp1 cp2 vbb vbb 56 v full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 package outline drawings for reference only ? not for tooling use (reference jedec mo-220wggd) dimensions in millimeters not to scale exact case and lead con?guration at supplier discretion within limits shown 0.95 c seating plane c 0.08 21x 20 20 2 1 1 2 20 2 1 a a b c d d c 4.00 0.15 2.45 4.00 0.15 2.45 4.10 0.30 0.50 4.10 0.75 0.05 0.50 bsc 0.40 0.25 2.45 2.45 b pcb layout reference view terminal #1 mark area exposed thermal pad (reference only, terminal #1 identi?er appearance at supplier discretion) reference land pattern layout (reference ipc7351 qfn50p400x400x80-21bm); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) coplanarity includes exposed thermal pad and terminals +0.05 ?0.07 +0.15 ?0.10 es package, 20-pin qfn with exposed thermal pad full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 for reference only ? not for tooling use (reference mo-153 act) not to scale dimensions in millimeters exact case and lead con?guration at supplier discretion within limits shown d 1 3.00 4.20 a b 0.45 1.70 20 21 b 6.10 0.65 c d exposed thermal pad (bottom surface) branding scale and appearance at supplier discretion a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 20x 0.65 bsc 0.25 bsc 21 20 6.50 0.10 4.40 0.10 3.00 4.20 6.40 0.20 gauge plane seating plane c pcb layout reference view nnnnnnn yyww lllllll standard branding reference view n = device part number = supplier emblem y= last two digits of year of manufacture w = week of manufacture l= lot number terminal #1 mark area reference land pattern layout (reference ipc7351 sop65p640x110-21m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) lp package, 20-pin etssop with exposed thermal pad full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 copyright ?2015, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision C february 12, 2015 initial release 1 july 14, 2015 updated functional block diagram (page 1); added packing information (page 2); changed references to lss to sense. full-bridge pwm gate driver A4956 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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